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From STDFGroup
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Overview
This site is a place for users of Semicondutor test results to collaborate on a standard format for logging scan fails and memory fails in STDF.
The Group, comprised of representatives from leading ATE and EDA providers, along with several of the world's largest semiconductor manufacturers, was started after meetings initiated by Verigy at Semicon West 2006. It recently added IBM, Texas Instruments, and Advantest to its growing list of participating companies. The Group is targeting initial internal test trials of the standard this fall, with a Beta site evaluation program planned for late 2007. This effort was recognized by all as a key step to improving ASIC yield ramp efforts.
Chair: Ajay Khoche (akhoche@gmail.com)
Co-Chair: John Rowe (jdotrowe@gmail.com)
Wiki setup/maintenance Mary Israni (mary@nanoisi.com)
Questions? Please contact akhoche@gmail.com
Please find a copy of Press Release 
here 
Public Face-2-Face Meetings
STDF Datalog General Documents and Presentations
Spec Documents
STDF Version 4-2007.1 Specification
STDF Version 4-2007 Specification
The Next Step in Volume Scan Diagnosis
Scan Fail Datalog Standard
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Next meeting: Meetings are now held on a need basis, The group is doing dployment discussions currently
Audio conf. number:
US:1-866-209-8933
Europe: France 438-030-257 (Grenoble) 1-6982-6861 (Paris) Germany 7031-204-8020
Mtg ID: *3547091*
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The sub-committee has finished incorporating the feedback from the
ballot review. Please see see the latest draft below
The ballot draft and the ballot form can be found below
Ballot Comments and Resolutions
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Review Document
RecordMapping Sub-group meeting Notes
Meeting Notes
Discussion Documents
Pkg_ID_req Synopsys_ATPG_term Inovys_ATPG_term
Inovys_File_identification
DataModel Freescale_Darrel PhilExample
Documents Foe 5-22-2007 Meeting
May22Presentation-withComments-Ajay
Draft Proposals
Infineon, Veriy, Mentor Proposal ST Proposal ST Proposal Notes
Memory Fail Datalog
The group is currently reviewing the first draft. The current outstanding issues w.r.t.
the draft are in 
this document
The Group has prepared the first draft proposal which is available here
It is currently being discussed and reviewed by the committee.
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Next meeting: 8th Jan 2009 10.00AM-11.00AM (PT);
Audio conf. no:
US:1-866-209-8933
Europe: France 438-030-257 (Grenoble) 1-6982-6861 (Paris) Germany 7031-204-8020
mtg ID *3547091*
Web Conference Info
1) Go to http://conference.verigy.com
2) Enter the Conference ID that will be give during the call in the Conference ID field
3) Type is your name
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Availble Drafts
Bitmap Test Data in STDF File -STMicroelectronics
Meeting Notes
2010
No meeting on April 8th
2009
Mem-Jan22_2009 
Jan 22 discussions Docs
2008
2008-6-12 - No Mtg
2008-5-29 - No mtg
2007
Mem-July12_2007 Mem-July26_2007
Mem-June14_2007 Mem-June28_2007
Mem-Apr 19, 2007 Mem-Apr 5, 2007
Mem-Mar 22, 2007 Mem-Mar 8, 2007
Mem-Jan 25, 2007 Mem-Jan 11, 2007
Discussion Documents
2009_3_26:Direct Access Record Structure Presentation - Ajay
2009_2_26:Record Structure Presentation - Ajay
2008_6_24:Embedded Memory Semicon Presentation - Ajay
2008_6_24:Embedded Memory BitMap Proposal- Ajay
PDF Memory Orientation scheme - Thomas
2008_5_1:Embedded Memory BitMap Proposal- Ajay
2008_1_24:Embedded Memory BitMap Proposal- Ajay
2008_1_10:Embedded Memory BitMap Proposal- Ajay
2007_12_12:Embedded Memory BitMap Proposal- Ajay
2007_11_1:Embedded Memory BitMap Proposal- Ajay
2007_11_1:Embedded Memory BitMap Proposal- FreeScale
Frame Format Standard Proposal
Emem Comparison Table Frame Communication Protocols
Embedded Memory Diag Frame Fields - Virage
Embedded Memory Diag Frame Fields - ARM
Embedded Memory Diag Frame Fields - Mentor
QC_Bitmap_req ARM_Bitmap_req
Mentor_Bitmap_req
YieldDynamicsReq
VirageLogic_bitmap_Req Scan_faillog_datamodel
